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general description the max14001/max14002 are isolated, single-channel analog-to-digital converters (adcs) with programmable voltage comparators and inrush current control optimized for configurable binary input applications. 3.75kv rms of integrated isolation is provided between the binary input side (field-side) and the comparator output/spi-side (logic-side) of the max14001/max14002. an integrated, isolated, dc-dc converter powers all field-side circuitry, and this allows running field-side diagnostics even when no input signal is present. the 20-pin ssop package provides 5.5mm of creepage and clearance with group ii cti rating. these devices continually digitize the input voltage on the field-side of an isolation barrier and transmit the data across the isolation barrier to the logic-side of the device where the magnitude of the input voltage is compared to programmable thresholds. the binary comparator output pin is high when the input voltage is above the upper threshold and low when it is below the lower threshold. response time of the comparator to an input change is less than 150s with filtering disabled. with filtering enabled, the comparator uses the moving average of the last 2, 4, or 8 adc readings. both filtered and unfiltered adc readings are available through the 5mhz spi port, which is also used to set comparator thresholds and other device configuration. the max14001/max14002 control the current of a binary input through an external, high-voltage fet. this current cleans relay contacts and attenuates input noise. an inrush comparator monitoring the adc readings triggers the inrush current, or wetting pulse. the inrush trigger threshold, current magnitude, and current duration are all programmable in the max14001 but are fixed in the max14002. when the high-voltage fet is not providing inrush current, it switches to bias mode. bias mode places a small current load on the binary input to attenuate capacitively coupled noise. the level of bias current is programmable between 50a and 3.75ma in both the max14001 and max14002. this allows optimization of the tradeoff between noise attenuation and power dissipation. benefts and features enables robust detection of binary inputs ? programmable input bias current rejects line noise ? 3.75kv rms of isolation for 60 seconds ? 5.5mm of creepage and clearance ? group ii cti package material reduces bom and board space through high integration ? 10-bit, 10ksps adc ? binary threshold comparators ? control circuit for driving a depletion mode fet ? isolation for both data and dc-dc supply ? 20-ssop package increases equipment up time and simplifies system maintenance ? enables field-side diagnostics ? automatic self-diagnostics provides unparalleled flexibility ? programmable upper and lower input thresholds ? programmable inrush current activation threshold, magnitude, and duration ? daisy-chainable spi interface applications high-voltage binary input (12vC300v) distribution automation substation automation industrial control, multi-range, digital input modules with individually isolated inputs safety regulatory approvals (pending) ul according to ul1577 ordering information appears at end of data sheet. 19-8514; rev 0; 5/16 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs evaluation kit available
v ddl to gndl ......................................................... -0.3v to +6v v dd to gndl .......................................................... -0.3v to +6v logic-side inputs ( cs , sclk, sdi, fault ) to gndl ................................................................................ -0.3v to +6v logic-side outputs (sdo, cout) to gndl .............................................. -0.3v to (v ddl + 0.3v) v refin , v ain to agnd ........................................... -0.3v to +2v agnd to gndf .................................................... -0.3v to +0.3v gate to gndf ........................................................ -0.3v to +4v ifet to gndf ....................................................... -0.3v to +12v iset to gndf ......................................................... -0.3v to +2v v ddf to gndf ........................................................ -0.3v to +6v short-circuit duration ( fault , cout, sdo to gndl or v dd ) ................ continuous continuous power dissipation (t a = +70c) 20-pin ssop .............................................................. 952.4mw operating temperature range ......................... -40c to +125c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c 20-pin ssop junction-to-ambient thermal resistance ( ja ) .......... 84c/w junction-to-case thermal resistance ( jc ) ............... 32c/w (note 1) (v ddl - v gndl = 1.71v to 5.5v, v dd - v gndl = 3.0v to 3.6v, r iset = 120k?, t a = -40c to +125c, v gndf = v gndl . typical values are at t a = +25c with v ddl = v dd = +3.3v, r iset = 120k?, v gndf = v gndl .) (notes 2, 3) maxim integrated 2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics parameter symbol conditions min typ max units power supplies logic power supply v ddl 1.71 5.5 v logic supply current i ddl v ddl = 3.3v, no load, cs = high 0.7 1.5 ma isolated dc-dc power supply input voltage v dd 3.0 3.3 3.6 v isolated dc-dc supply input current i dd v dd = 3.3v 4.8 8 ma logic power-up delay 0.2 ms field power-up delay c vddf = 0.1f 1 ms field power supply v ddf c vddf = 0.1f, unregulated output voltage 2.5 3.0 3.5 v gate charge pump voltage v gate 1a pull-down 3 3.6 4 v logic-side undervoltage lockout threshold v uvlol v dd 3v 1.5 1.6 1.66 v v uvlod v ddl 1.71v 2.69 2.82 2.95 v logic-side undervoltage lockout threshold hysteresis v uvlhyst 50 mv v uvdhyst 100 mv field-side undervoltage lockout threshold v uvlof (note 4) 1.95 2.1 2.25 v max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
(v ddl - v gndl = 1.71v to 5.5v, v dd - v gndl = 3.0v to 3.6v, r iset = 120k?, t a = -40c to +125c, v gndf = v gndl . typical values are at t a = +25c with v ddl = v dd = +3.3v, r iset = 120k?, v gndf = v gndl .) (notes 2, 3) maxim integrated 3 electrical characteristics (continued) parameter symbol conditions min typ max units field-side undervoltage lockout threshold hysteresis v uvfhyst 100 mv protection esd any pin to gndl or gndf inclusive 2 kv eft (burst) system-level requirement iec 61000-4-4 common mode (note 5) 3 kv dynamic common-mode transient immunity cmti (note 6) 50 kv/s adc and comparator input voltage range v ain nominal measurement range 0 v refin (1.25) v reference input range v refin 1.15 1.25 1.35 v adc resolution 10 bits gain error ge v in = 98% v ref , excluding offset error and reference errors -0.55 +0.55 % offset error oe v in = 2% v ref , offset calculated -0.2 +0.2 %fs differential nonlinearity dnl 1 lsb integral nonlinearity inl included in the gain + offset window 1 lsb input leakage current iilr v ain = 1.25v -200 +200 na throughput 8 10 12 ksps latency (no filtering) ain step input to cout transition (notes 4, 7) 12 150 s latency (2 readings) ain step input to cout transition (notes 4, 7) 92 270 s latency (4 readings) ain step input to cout transition (notes 4, 7) 180 510 s latency (8 readings) ain step input to cout transition (notes 4, 7) 340 990 s internal voltage reference nominal output voltage 1.25 v output voltage accuracy over the entire temperature range -5 +5 % output voltage temperature drift t cvout 50 ppm/c external voltage reference reference voltage 1.15 1.25 1.35 v available bias current when powered from v ddf (series) or refin (shunt) 70 a max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
(v ddl - v gndl = 1.71v to 5.5v, v dd - v gndl = 3.0v to 3.6v, r iset = 120k?, t a = -40c to +125c, v gndf = v gndl . typical values are at t a = +25c with v ddl = v dd = +3.3v, r iset = 120k?, v gndf = v gndl .) (notes 2, 3) maxim integrated 4 electrical characteristics (continued) parameter symbol conditions min typ max units bias current dac full-scale current excludes r iset errors 3.375 3.75 4.125 ma resolution 0.25 ma offset error ibias[3:0] = 0 (see cfg register) 50 100 a integral nonlinearity inl 0.25 lsb inrush current dac full-scale current excludes r iset errors 94.5 105 115.5 ma resolution 7 ma offset iinr[3:0] = 0 (see inrp register) 50 100 a integral nonlinearity inl 0.25 lsb inrush current max14002 only. excludes r iset errors 44.1 49 53.9 ma inrush timer range nominal 0 120 ms resolution programmed by tinr[3:0] (see inrp register) 8 ms error -20 +20 % maximum duty cycle du1 = 0, du0 = 1 (see inrp register) 1.6 % du1 = 1, du0 = 0 (see inrp register) 3.1 du1 = 1, du0 = 1 (see inrp register) 6.3 inrush duration max14002 only 38.4 48 57.6 ms inrush comparator range 0 adc fs v resolution 10 bits latency (no filtering) from input voltage = inrt until iinr = 50% of set value (notes 4, 7) 22 160 s latency (2 readings) from input voltage = inrt until iinr = 50% of set value (notes 4, 7) 102 280 s latency (4 readings) from input voltage = inrt until iinr = 50% of set value (notes 4, 7) 192 520 s latency (8 readings) from input voltage = inrt until iinr = 50% of set value (notes 4, 7) 356 1000 s logic i/o levels input high voltage v ih sclk, sdi, cs 0.7 x v ddl v input low voltage v il sclk, sdi, cs 0.3 x v ddl v input hysteresis v hyst sclk, sdi, cs 0.05 x v ddl v max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
(v ddl - v gndl = 1.71v to 5.5v, v dd - v gndl = 3.0v to 3.6v, r iset = 120k?, t a = -40c to +125c, v gndf = v gndl . typical values are at t a = +25c with v ddl = v dd = +3.3v, r iset = 120k?, v gndf = v gndl .) (notes 2, 3) note 2: all devices are 100% production tested at t a = +25c. specifications for all temperature limits are guaranteed by design. note 3: all currents into the device are positive; all currents out of the device are negative. all voltages are referenced to their respective ground (gndl or gndf), unless otherwise noted. note 4: guaranteed by characterization; not production tested. note 5: eft voltage according to iec 61004-4 is tested through direct coupling to the generator. note 6: cmti is the maximum sustainable common-mode voltage slew rate while maintaining the correct output states. cmti applies to both rising and falling common-mode voltage edges. tested with the transient generator connected between gndf and gndl (v cm = 1000v). note 7: latency numbers are based on the following condition: a full-scale step is applied at the adc input and thu is set to mid-scale value (0x1ff). latency is the delay from the step at the adc input to the digital comparator output. maxim integrated 5 electrical characteristics (continued) parameter symbol conditions min typ max units output high voltage v oh sdo, cout, sourcing 4ma v ddl - 0.4 v output low voltage v ol sdo, cout, fault , sinking 4ma 0.4 v output high-impedance leakage current i ol sdo, fault -1 +1 a input leakage current i il sclk, sdi, cs -1 +1 a input capacitance c in sclk, sdi, cs , f = 1mhz 2 pf spi timing characteristics sclk clock frequency f sclk single device 5 mhz sclk clock period t sclk single device 200 ns sclk pulse-width high t sclkh single device 80 ns sclk pulse-width low t sclkl single device 80 ns cs fall-to-sclk rise time t cs(lead) 80 ns sclk fall-to- cs rise time t cs(lag) 80 ns sdi hold time t dinh 40 ns sdi setup time t dinsu 40 ns sdo enable time ( cs falling to sdo valid) t dout(en) c l = 50pf 40 ns sdo disable time ( cs rising to sdo three- state) t dout(dis) c l = 50pf 40 ns output data propagation delay t do c l = 50pf. sclk falling-edge to sdo valid 50 ns write-command to field implementation delay t fid from cs de-assertion until feld-side registers are loaded 165 ns inter-access gap t iag minimum time cs must be de-asserted between commands 920 ns max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
note 8: v iso , v iowm and v iorm are defined by the iec 60747-5-5 standard. note 9: product is qualified v iso for 60 seconds. 100% production tested at 120% of v iso for 1s. note 10: capacitance is measured with all pins on field-side and logic-side tied together. maxim integrated 6 insulation characteristics parameter symbol conditions value units partial discharge test voltage v pr method b1 = v iorm x 1.875 (t = 1s, partial discharge < 5pc) 1050 v p maximum repetitive peak isolation voltage v iorm (note 8) 560 v p maximum working isolation voltage v iowm continuous rms voltage (note 8) 400 v rms maximum transient isolation voltage v iotm t = 1s 6300 v p maximum withstand isolation voltage v iso t = 60s, f = 60hz (notes 8, 9) 3.75 kv rms maximum surge isolation voltage v iosm basic insulation, 1.2/50s surge pulse per iec 61000-4-5 7.5 kv insulation resistance logic-to-field r s t a = +125c, v io = 500v >10 9 barrier capacitance logic-to-field cio f = 1mhz (note 10) 10 pf minimum creepage distance cpg ssop 5.5 mm minimum clearance distance clr ssop 5.5 mm internal clearance distance through insulation 0.015 mm comparative tracking resistance index cti material group ii (iec 60112) >400 climatic category 40/125/21 pollution degree (din vde 0110, table 1) 2 safety regulatory approvals (pending) ul the max14001/max14002 are certifed under ul1577. rated up to 3750v rms isolation voltage for basic insulation. max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
(v ddl = v dd = +3.3v, r iset = 120k?, isolated gndf and gndl, high-voltage fet is ixty08n100d2, with t a = +25c unless otherwise noted.) maxim integrated 7 typical operating characteristics 400s/div v gate startup c gate = 0.01f v dd = 0 - 3v step v gate 1v/div v dd 1v/div toc04 3.35 3.4 3.45 3.5 3.55 3.6 0 1 2 3 4 5 6 v gate voltage (v) current load (a) v gate voltage vs. current load toc05 2.6 2.7 2.8 2.9 3 3.1 3.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 v ddf voltage (v) temperature ( c) v ddf voltage vs. temperature i load = 0a i load = 70a toc06 1.1875 1.2125 1.2375 1.2625 1.2875 -40 -25 -10 5 20 35 50 65 80 95 110 125 reference voltage (v) temperature ( c) internal voltage reference vs. temperature toc01 1.1875 1.2125 1.2375 1.2625 1.2875 2.3 2.6 2.9 3.2 3.5 3.8 reference voltage (v) v ddf voltage (v) internal voltage reference vs. v ddf voltage toc02 200s/div v ddf startup v dd = 0 - 3v step c vddf = 0.1f||1000pf v dd 1v/div v ddf 1v/div toc03 2 . 9 8 2 . 9 9 3.00 3 . 0 1 3 . 0 2 3 . 0 3 3 . 0 4 3 . 0 5 3 . 0 6 3 . 0 7 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 v d d f v ol t a g e ( v ) cur r e n t l o a d ( a ) v d d = 3v v d d = 3. 3 v v d d = 3. 6 v v d d f v o l t a g e v s . cu r re n t l o a d t a = 25c t o c 07 0 . 5 7 0 . 5 8 0 . 5 9 0 . 6 0 . 6 1 0 . 6 2 - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 v i se t v o l t a g e ( v ) te m pe r a t ur e ( c ) v i se t v o l t a g e vs . t e mpe r a t ur e 120 k r es i s to r o n i se t p in t oc 08 www.maximintegrated.com max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs
(v ddl = v dd = +3.3v, r iset = 120k?, isolated gndf and gndl, high-voltage fet is ixty08n100d2, with t a = +25c unless otherwise noted.) maxim integrated 8 typical operating characteristics (continued) -5 -4 -3 -2 -1 0 1 2 3 4 5 7 21 35 49 63 77 91 105 error (%) inrush current (ma) inrush current error t a = - 40c t a = +125 c t a = +25 c toc12 49.5 50 50.5 51 51.5 52 52.5 53 53.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 input bias current (a) temperature ( c) input bias current vs. temperature cfg: ibias = '0000' toc09 1ms/div inrush current vs. time tinr = '0001' (8ms) iinr = '0111' (49ma) ibias = '0001' (0.25ma) inrt = 0x021 (9.68v) voltage mode v in 5v/div i iinr 20ma/div toc14 1 . 4 7 1 . 47 5 1 . 4 8 1 . 48 5 1 . 4 9 1 . 49 5 1 . 5 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 i n p u t b i as curr e n t ( m a ) i n p u t v o l t a g e ( v ) i n p u t b i a s cur r e n t vs . i n p u t v o l t a g e c f g:i b i as = ' 0110 ' ( d efault) t oc 10 -6 -4 -2 0 2 4 6 0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75 error (%) input bias current (ma) input bias current error t a = - 40c t a = +125 c t a = +25 c toc11 1ms/div inrush current vs. time tinr = '0001' (8ms) iinr = '0111' (49ma) ibias = '0001' (0.25ma) inrt = 0x1fe (149.56v) voltage mode i iinr 20ma/div v in 100v/div toc15 1ms/div inrush current vs. time tinr = '0001' (8ms) iinr = '0111' (49ma) ibias = '0001' (0.25ma) fast mode v in 5v/div i iinr 20ma/div toc13 www.maximintegrated.com max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs
(v ddl = v dd = +3.3v, r iset = 120k?, isolated gndf and gndl, high-voltage fet is ixty08n100d2, with t a = +25c unless otherwise noted.) maxim integrated 9 typical operating characteristics (continued) 1 0 0 s/ d i v c o u t c h a n g e o n r i s i n g e d g e d e fa u l t r e g i s te r s e tti n g s th u = 0 x2 0 0 ( 0 . 6 2 5 v ) v a i n = 0 - 1 v s te p c o u t 1 v / d i v v a i n 1 v / d i v t oc 18a 1 0 0 s/ d i v c o u t c h a n g e o n f a l l i n g e d g e d e fa u l t r e g i s te r s e tti n g s th l = 0 x1 0 0 ( 0 . 3 1 3 v ) v a i n = 1 - 0 v s te p c o u t 1 v / d i v v a i n 1 v / d i v t oc 18b 4 0 0 s/d i v i n p u t b i a s c u r r e n t a t s t a r t u p m e a s u r e d a c r o s s 1 0 k r e s i s t o r in s e r ie s w ith exte rn a l fe t v i n = 3 0 0 v v d d = v d d l = 0 - 3 . 3 v s tep v d d / v d d l 1 v /d i v v i b i a s 2 0 0 m v /d i v t oc 1 6 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 128 256 384 512 640 768 896 1024 inl (lsb) output code (decimal) integral nonlinearity vs. code t a = +25 c toc17 44 45 46 47 48 49 50 -40 -25 -10 5 20 35 50 65 80 95 110 125 inrush time (ms) temperature ( c) inrush timer vs. temperature inrp:tinr = '0110' (48ms) toc19 www.maximintegrated.com max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs
maxim integrated 10 pin confguration pin description 2 0 1 9 1 8 1 7 1 6 1 5 1 3 1 2 3 4 5 6 8 v dd l g ndl fa u l t cout a gn d a i n g ndf i se t top v ie w m a x 14001 m a x 14002 c s s c l k s d o ga te i c 1 4 7 s d i i fe t 1 1 1 0 g ndl g ndf 1 2 9 v d d v dd f r e fi n 2 0 - ss o p 7 . 3 3 m m 7 . 9 m m pin name reference function power supply 20 v ddl gndl power input for the logic-side of the max14001/max14002. bypass with 10f||1000pf capacitors to gndl. 12 v dd gndl power input for the isolated dc-dc converter. the dc-dc converter powers the feld- side of the max14001/max14002. bypass with 10f||1000pf capacitors to gndl. 11, 19 gndl power and signal ground for all logic-side pins. 9 v ddf gndf unregulated output of the dc-dc converter. bypass to gndf with 0.1f||1000pf capacitors. the 1000pf capacitor should be placed as close to the pin as possible. 8 gate gndf bias voltage for the gate of the external depletion mode fet. connect a 0.01f capacitor from gate to gndf. 2, 10 gndf field-side ground for everything except the adc front-end and voltage reference. analog 1 iset gndf connect a 120k? resistor from iset to gndf. this generates a reference current used to establish the correct bias and inrush currents. parasitic capacitance on this pin should not exceed 10pf. 7 ifet gndf current sink input for inrush and bias current. this pin is buffered from high voltage by connecting it to the source of the external high-voltage fet. connect a 1000pf capacitor from ifet to gndf. 3 ain agnd analog input. the adc measures the voltage on this pin with respect to agnd. 4 agnd analog ground reference for ain and refin 5 refin agnd optional external voltage reference input (nominally 1.25v). when an external reference is used, connect a 0.1f bypass capacitor from refin to agnd. when an internal reference is used, connect refin directly to agnd. 6 ic gndf internally connected. connect to gndf. max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
maxim integrated 11 pin description (continued) pin name reference function digital 18 fault gndl open-drain output that asserts low during a number of different error conditions. the cause of the error is latched in the flags register. see diagnostic and fault reporting features for details on clearing fault . 17 cout gndl digital comparator output. cout is high when ain is above the upper threshold (thu) and low when ain is below the lower threshold (thl). 16 cs gndl chip select for spi interface. assert low to enable spi functions and sdo. sdo is high impedance when cs is high. 15 sclk gndl serial clock for spi interface 14 sdi gndl serial data input for spi interface (mosi) 13 sdo gndl serial data out for spi interface (miso) functional diagram 3 . 6 v 60 0 m v fi e ld s i d e log i c s i d e 1 0 - b i t a d c i n te rn a l v r e f 1 . 2 5 v c on tr ol r e gi s te r p ow e r d c - d c r e fi n a i n a gn d ga te i fe t i se t i c v i n c ou t fa u l t c s s c l k s d i s d o v dd f g ndf v d d g ndl v dd l 12 0 k 0 . 0 1 f 100 0 p f m a x 1400 1 / m a x 1400 2 curr e n t s i n k i n g d a c l og i c a n d sp i i n te r fa c e d a ta r e c e i ve r b i n a r y c om p i nru s h c om p c fg : ex r f max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
detailed description the max14001/max14002 are 10-bit adcs with a 3.75kv rms isolated spi interface. additional features include a programmable magnitude comparator, programmable inrush current for cleaning relay contacts, and programmable input bias current to optimize power dissipation while reducing capacitively coupled input noise. the adc and all field-side circuits are powered by an integrated, isolated, dc-dc converter that allows field-side functionality to be verified even when there is no input signal or other field-side supply. this makes the max14001/max14002 ideally suited for high density, multi-range, individually isolated, binary input modules. adc the devices adc employs a 10-bit sar architecture with a nominal sampling rate of 10ksps, and has an input voltage range of 0v to +1.25v with respect to agnd. after power-up, the adc runs continually at the nominal sampling rate. the 10-bit unfiltered adc reading and filtered adc reading are both available via the spi interface. filtering averages the most recent 2, 4, or 8 readings depending on the value of the ft[1:0] bits in the cfg register. a binary comparator responds within 150s to changes in input voltage by continually comparing the latest adc reading to the programmed thresholds (refer to the ec table for response times when using the adc filter). when the latest adc reading is higher than the upper threshold (thu), the comparators output pin (cout) is high and when it is lower than the lower threshold (thl), the comparators output pin (cout) is low. internal/external voltage reference confguration the max14001/max14002 feature both internal and external voltage reference capability. the 1.25v internal reference has a maximum error of 5% over the entire operating temperature range. if higher accuracy is required, an external reference may be used. the external reference may be either series or shunt, but must not draw more than 70a of supply current. series references must be powered from v ddf while shunt references are powered from an internal 70a current source that is connected to the refin pin. internal/external voltage reference mode is selected using the spi interface to program the cfg register. refer to table 1 for the cfg register configuration, figure 1 for shunt reference hardware connection, and figure 2 for series reference hardware connection. figure 1. shunt voltage reference connection figure 2. series voltage reference connection maxim integrated 12 f i e l d s i d e g n d f v d d f r e fi n a gn d m a x 140 0 1 / m a x 140 0 2 e x te r n a l v r e f 1 . 2 v n om i n a l s hu n t v ol ta ge r e fe r e n c e 0 . 1 f r e gi s t e r c on fi gu r a ti on c fg e x r f 1 c fg e x ti 1 a gn d gn d f 10 0 0 f 0 . 1 f fi e ld s i d e g nd f v dd f r e fi n a g n d m a x 1400 1 / m a x 1400 2 exte rn a l v r e f 1 . 2 v n o m i n a l ser i es v o l ta g e r e fe r e nc e r e g i s te r c o n fi g ur a ti o n c fg exr f 1 c fg exti 0 i n o u t g n d 0 . 1 f a g n d 100 0 f 0 . 1 f g nd f max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
adc error the uncalibrated error of the adc lies within the window shown in the figure 3 adc error window. the boundaries of the box are defined by the offset and gain error from the ec table and include inl errors as well as drift over temperature. the upper-boundary is set by the most positive offset combined with the most positive gain error. conversely, the lower-boundary is set by the most negative offset combined with the most negative gain error. error max = oe fs + v in x ge where oe is the offset error in %fs, fs is the full scale voltage, v in is the input voltage being measured, and ge is the gain error in %. if a resistor-divider is used in front of the adc, fs and v in can be the voltages at the input of the divider. for total system error, the resistive-divider error and the error of the voltage reference in percent are added to the gain error of the adc. system error max = oe fs + v in x (ge + error r + error vref ) where oe is the offset error in %fs, fs is the full scale voltage, v in is the input voltage being measured, ge is the gain error in %, error r is the resistive-divider error in %, and error vref is the voltage reference error in %. for example, assume: all errors specs are symmetrical. ? |maximum positive error| = |maximum negative error| the input resistive-divider is made of 1% resistors and divides the binary voltage by a nominal factor of 240. ? maximum resistive-divider error error r = 2% a nominal 1.25v reference with an error of 5% ? full-scale input voltage f s = 1.25v x 240 = 300 ? error vref = 5% adc offset error oe = 0.3% adc gain error ge = 0.3% input voltage v in = 200v system error max = 0.3% x 300v + v in x (0.3%+2%+5% ) when v in = 200v, the maximum error is 15.5v. if the comparator threshold is set at 200v (adc reading of decimal 682), the comparator could trip with a voltage as low as 184.5v or as high as 215.5v. conversely, if the adc is to read 682, the nominal input voltage would be 200v, but the actual voltage could be as high a 215.5v or as low as 184.5v. table 1. voltage reference register configuration figure 3. adc error window (excludes v ref error) maxim integrated 13 reference configuration cfg:exrf cfg:exti connection internal reference 0 0 connect refin directly to agnd. external series reference 1 0 series reference is supplied by v ddf . output is connected to the refin pin. bypass refin to agnd with a 0.1f capacitor. external shunt reference 1 1 internal current source is turned on. shunt reference is connected between refin and agnd. bypass refin to agnd with a 0.1f capacitor. -10 -8 -6 -4 -2 0 2 4 6 8 10 0.00 0.20 0.40 0.60 0.80 1.00 1.20 e r r o r ( m v ) v a i n ( v ) u pper er r o r l i m i t l o wer er r o r l i m i t max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
high-voltage fet current control the devices control a high-voltage depletion mode fet that can be used to sink inrush current for cleaning relay contacts while contacts are closing, or a smaller bias current for input noise suppression while contacts are open. when the inrush pulse is finished, the fet current is reduced to the bias level, lowering power dissipation in the fet while still providing an input load. inrush cur - rent is fixed in the max14002 (49ma for 48ms) but is configurable in the max14001. the max14001s inrush current magnitude and duration are both programmable: the magnitude ranges from 50a to 105ma in 7ma increments, and the duration ranges from 0ms to 120ms in 8ms increments. bias current is adjustable in both the max14001 and max14002, and ranges from 50ua to 3.75ma in 0.25ma increments. the max14001s inrush pulse can be initiated in one of two ways: voltage triggered inrush mode based on the adc reading or fast inrush mode based on the high- voltage fet current level. in voltage triggered inrush mode (fast bit in the cfg register = 0), the pulse is initiated when the adc reading equals or exceeds the programmed trigger threshold in the inrt register. once an inrush pulse has been triggered, the adc read - ing must drop below the re-arm threshold in the inrr register before another inrush pulse can be triggered. in fast mode (fast bit in the cfg register = 1), the inrush pulse starts as soon as the input signal is able to supply the inrush current. re-arming occurs when the input no longer supplies enough current to the high-voltage fet (either inrush or bias current depending on the present mode). the max14002 operates in fast mode only. figure 4 and figure 5 illustrate the two methods for trig - gering a pulse of inrush current. voltage mode a) the high-voltage fet is trying to sink bias current, but cannot because the input signal is not supplying enough current. b) when the input voltage increases to the inrush trigger threshold (inrt), the fet current is increased to the inrush level and the inrush timer is started. c) contact bounce causes the input voltage to drop below the inrush reset threshold (inrr). the fet current is reduced to the bias level and the inrush timer is reset. d) the input voltage again rises to the inrush trigger threshold. the fet current is increased to the inrush level and the inrush timer is started. e) the inrush timer expires and the fet current is reduced to the bias level. f) the input voltage drops below the inrush re-arm threshold (inrr). the inrush timer is reset and prepared to deliver the next inrush pulse. the fet current remains at the bias level. g) the noise pulse is fully clamped at the turn-on voltage of the fet circuit. h) higher energy noise pulse that is partially clamped by the bias current. noise current exceeds the bias current so the voltage rises above the turn-on voltage of the fet circuit. figure 4. voltage triggered inrush mode figure 5. fast inrush mode maxim integrated 14 i n pu t c u r r en t i n pu t vo l t ag e i n r t i n r r a b c d e f g h i n pu t c u r r en t i n pu t vo l t ag e 1 2 3 4 5 6 7 8 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
fast mode 1) the high-voltage fet is trying to sink the inrush current, but cannot because the input signal is not supplying enough current. since the current level cannot be met, the fet current is set to the inrush level, and the inrush timer is reset. 2) the input voltage increases and supplies enough current for the inrush pulse. the inrush timer is started. 3) the inrush timer expires and the fet current is reduced to the bias level. 4) the input voltage drops and can no longer supply the bias current. the inrush timer is reset and the fet current is set to the inrush level. 5) contact bounce raises the input voltage and supplies enough current for an inrush pulse. the inrush timer is started. 6) the input voltage drops and can no longer supply the inrush current. the inrush timer is reset and the fet current remains the inrush level. 7) the noise pulse is fully clamped at the turn-on voltage of the fet circuit. 8) higher energy noise pulse is fully clamped by the inrush current. noise current exceeds the bias current, but since the fet is trying to sink the larger input current, the input current rises and the voltage remains clamped at the turn-on voltage of the fet circuit. repetitive inrush pulse limiting (max14001 only) the max14001 can limit repetitive inrush pulses to prevent overheating from abnormal input signals that would otherwise trigger a continuous stream of inrush pulses. when the pulse limiting function is enabled, the max14001 monitors the percentage of time that the inrush current is flowing. when it exceeds the duty cycle threshold over the last 10 seconds, additional inrush pulses are disabled for the next 10 seconds. when the pulse limiting is triggered, the inrd bit in the flags register is set and fault is asserted if the einrd bit in the flten register is set. the pulse limiting function can be turned off or the pulse duty cycle can be set to 1.6%, 3.1%, or 6.3% using the du[1:0] bits in the inrp register. the max14002 does not provide a repetitive inrush pulse limiting feature. diagnostic and fault reporting features the max14001/max14002 continuously monitor seven possible fault conditions, and a hardware alert is provided via the open drain fault pin, which asserts low when an enabled fault is detected. the possible faults are: adc functionality error, repetitive inrush pulses being triggered, spi framing error, loss of internal isolated data stream, crc errors from internal communication, high-voltage fet failure, and corrupted memory error. the bits in the flten register determine how the fault output responds to the seven error conditions, and the fault output is asserted if the corresponding bit is enabled in the flten register. if the flten register bit dyen = 0, fault operates as a latched output and remains asserted until the flags register is cleared but if the bit dyen = 1, fault operates as a dynamic output and de-asserts when the faults are no longer detected even though bits in the flags register remain set. if the corresponding bit in the flten register is not set, when an error is flagged, fault will not be asserted, but the bit in the flags register will still be latched and remain set until the register is read, which automatically clears all bits in the flags register. note that if a fault condition still exists when the register is read, the cleared fault bit will immediately be set again . in a typical application, fault triggers an interrupt routine in the microcontroller or fpga, which will read the flags register to determine the cause of the interrupt. diagnostic conditions the diagnostic features implemented on the max14001/ max14002 can be summarized as follows: 1) adc functionality error: adc functionality is checked by looking for changes in the adc output. to ensure that a change should have occurred, a special test measurement is made while injecting a small cur - rent at the input of the adc. this special measurement used for adc functionality verifcation is interleaved between normal measurements and does not affect the adc sampling time. if the adc reading does not change, an adc functional failure is declared and bit adc (bit 1) in the flags register is set. 2) repetitive inrush pulses: if the repetitive inrush pulse limiting feature of the max14001 is turned on, and pulse limiting is triggered, bit inrd (bit 2) in the flags register is set. see repetitive inrush pulse limiting (max14001 only) for details on inrush pulse limiting. 3) spi framing error: after cs transitions from low to high, if the number of bits clocked in while cs was low is not an integer multiple of 16, an spi framing error is declared and bit spi (bit 3) in the flags register is set. the instruction in the spi shift register is not decoded and no register value is changed. 4) loss of data stream: the feld-side sends adc maxim integrated 15 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
data across the isolation barrier to the logic-side every 100s, except for the startup period. if the periodic feld-side data is not received, a loss of data stream fault is declared and bit com (bit 4) in the flags register is set. it is possible to recover from a loss of data stream fault by asserting a hard reset through the act register, which will return all of the registers to their default state, thus requiring the max14001/max14002 to go through the startup confguration process. 5) crc errors from internal communication: internal communication across the isolation barrier includes a crc code to ensure that corrupt data does not cause system problems. if the crc indicates an error, the received data is discarded. if six consecutive crcs fail, a crc fault is declared and bit crcl (bit 5) or crcf (bit 6) in the flags register is set. 6) high-voltage fet failure: if the adc reading is greater than the inrush re-arm threshold (inrr), and ifet is not able to sink the programmed current, a fet fault is declared and bit fet (bit 7) in the flags register is set. inrr is permanently set to 0x0c0 in max14002. 7) memory error: the devices continually compare the bits of each verifcation register to the bits of their corresponding confguration register. if any of the bits do not match, a memory fault is declared and bit mv (bit 8) in the flags register is set. no information on which register failed is provided. note that the default value for each verifcation register is the complement of its corresponding confguration register, which guarantees an mv fault any time power is lost and restored . fault at power-on the devices internal memory is volatile and must be reprogrammed after power cycling. to protect against undetected power glitches and the remote possibility that a memory bit would be lost during years of static operation, the devices monitor their configuration registers and assert bit mv (bit 8) in the flags register any time the memory is corrupted. verification registers have complementary por values compared to the configuration registers, and therefore the max14001/ max14002 start with a memory fault condition and assert the fault pin at startup. isolated power and data transfer a simplified view of the isolated power and data transfer sections is shown in the functional diagram . the logic-side supply v dd powers an integrated, inductively coupled, dc-dc converter that generates a nominal 3v with just enough output current to power the field-side of the max14001/max14002 and an external 70a voltage reference. no other circuits should be powered from the field-side of the max14001/max14002. serial data is transferred by capacitively-isolated differential transceivers. to verify reliable communication through the isolation barrier, a cyclic redundancy check (8-bit crc) is embedded in the transmitted serial data streams. if a crc fails, the data is discarded and no action is taken. if six consecutive crcs fail, the crc bit in the flags register is set and fault is asserted if the crc fault enable bit is set in the flten register. confguration and monitoring an spi interface is used for transferring configuration, control and diagnostic data as well as adc readings between a master (fpga or microcontroller) and single/ multiple max14001/max14002(s). the interface can support daisy-chain configuration and consists of four ports: sclk, cs , sdi and sdo. spi interface spi communication includes the following features: support for daisy-chain operation able to verify the previous command was correctly received by reading sdo on the next instruction cycle able to read/verify all written registers (except act register) identify when commands are not a multiple of 16-bits and set the spi fault fag commands of all 0s or all 1s do not change any writable registers a single command cannot program both the confguration and verifcation register serial clock up to 5mhz the command is 16-bits in length and the structure of the 16-bit data is shown in the table 2 . table 2. spi command maxim integrated 16 address control data 5-bits a[4:0], msb to lsb w/ r bit, read = 0, write = 1 10-bits d[9:0], msb to lsb max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
the first bit clocked into the sdi port is d[0], the data lsb ( note: many spi products clock msb first so the microcontroller or fpga needs to reverse data prior to outputting it to the max14001/max14002 sdi pin ). as long as cs is in a logic-low state, the spi interface is working as a simple shift register, and sdi data is shifted on the rising edge of sclk without decoding the commands. when cs goes back to logic-high state, the bits in the shift register are decoded. if the command is a write, the data portion of the spi shift register is copied to the specified register and the shift register is unchanged. if the command is a read, the content of the specified register is copied to the data portion of the spi shift reg - ister, while the address bits a[4:0] and control bit w/ r are unchanged. the read action is completed during the next instruction cycle when cs again goes to logic-low state and the contents of the shift register are clocked out of sdo on the falling edge of sclk. the functionality of each spi pin can be summarized as follows. serial clock (sclk): input for the master serial clock signal. the clock signal determines the speed of the data transfer (5mhz maximum) and all data transfers are synchronous to this clock. sclk must remain low when cs transitions are from high to low and from low to high. the number of sclk rising edges that are received during cs logic-low state must be a multiple of 16. otherwise, the received command will be ignored. chip select ( ): the cs input enables the spi interface. during a logic-low state, data is transferred on the edges of sclk. a logic-high state on cs forces sdo to high impedance mode and any sclk transitions are ignored. during a write cycle, the content of the shift register is transferred to the addressed internal register on the rising edge of cs . during a read cycle, the content of the internal register that was addressed is transferred to the shift register on the rising edge of cs and the data will be clocked out of the sdo pin during the next spi cycle. serial input (sdi): sdi or mosi is the serial input port of the spi shift register and data is clocked lsb first into the shift register on the rising edge of sclk. on the rising edge of cs , the input data is latched into the internal registers. serial output (sdo): sdo or miso is the serial output port of the spi shift register, and is in a high impedance state until the cs pin goes to logic-low state. data is clocked lsb first out of the shift register on the falling edge of sclk. the spi interface read and write timing diagrams are shown in figure 6 , figure 7 , and figure 8 . figure 6. spi write maxim integrated 17 c s s c l k s d i s d o d 0 d 1 d 2 d 7 d 8 d 9 w * a 0 a 1 a 2 a 3 a 4 . . . x x x x x x w * a 0 a 1 a 2 a 3 a 4 . . . h i gh - z h i gh - z 1 2 3 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 * w = 1 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
figure 7. spi read figure 8. spi timing diagram maxim integrated 18 cs sclk sdi sdo 1 2 3 8 9 10 11 12 13 14 15 16 1 2 3 8 9 10 11 12 13 14 15 16 0 0 0 0 0 0 r * a 0 a 1 a 2 a 3 a 4 0 0 0 0 0 0 r * a 0 a 1 a 2 a 3 a 4 r * a 0 a 1 a 2 a 3 a 4 d 0 d 1 d 2 d 7 d 8 d 9 r * a 0 a 1 a 2 a 3 a 4 high - z x x high - z x x x x high - z * r = 0 cs sclk sdi sdo d 0 d 1 d 9 w / r * a 0 a 1 a 2 a 3 a 4 ... a 0 a 1 a 2 a 3 a 4 x x high - z high - z 1 2 16 15 14 13 12 11 10 t sclk t sclkl t sclkh t cs ( lead ) t cs ( lag ) t dinsu t dinh t dout ( en ) t dout ( dis ) t do t iag ... ... x w / r * field t fid * r = 0 , w = 1 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
daisy-chain spi operation the device supports daisy-chain operation, allowing control/monitoring of multiple max14001/max14002 devices from a single serial interface host with common cs and sclk signals as illustrated in figure 9 . the data that is clocked into sdi is clocked out of sdo with a 16-sclk-cycle delay for each device in the daisy-chain, which is illustrated in figure 10 and figure 11 . figure 9. daisy-chain connection maxim integrated 19 r pull - up cs sclk sdi sdo max 14001 / 02 device 1 fault vddl cs sclk sdi sdo max 14001 / 02 device 2 fault vddl cs sclk sdi sdo max 14001 / 02 device n fault vddl ... ... cs miso mosi sclk micro - controller gpi vddl max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
figure 11. spi daisy-chain read figure 10. spi daisy-chain write maxim integrated 20 c s s c l k s d i 1 s d o 1 s d i 2 1 0 1 1 1 2 1 6 x a 0 n r n * h i gh - z s d o n - 1 s d i n .. . .. . 1 1 0 1 1 1 2 1 6 .. . .. . 1 .. . .. . a 4 n x a 0 1 r 1 * x .. . .. . a 4 1 h i gh - z x x x x a 0 2 x .. . .. . a 4 2 r 2 * * r = 0 1 6 1 0 1 1 1 2 1 6 .. . .. . 1 a 4 2 h i gh - z h i gh - z x a 0 3 r 3 * .. . .. . a 4 3 x h i gh - z x a 0 2 r 2 * x .. . .. . a 4 2 1 0 1 1 1 2 1 6 .. . .. . 1 a 0 2 r 2 * x .. . .. . a 4 2 x a 0 3 r 3 * x .. . .. . a 4 3 h i gh - z x a 0 n x .. . .. . a 4 n r n * h i gh - z s d o n h i gh - z x x h i gh - z x c s s c l k s d i 1 s d o 1 s d i 2 s d o n - 1 s d i n s d o n 1 0 1 1 1 2 1 6 .. . .. . 1 1 0 1 1 1 2 1 6 .. . .. . 1 x a 0 n r n * x .. . .. . a 4 n x a 0 2 r 2 * x .. . .. . a 4 2 x a 0 1 r 1 * x .. . .. . a 4 1 a 4 n a 4 1 d 0 1 a 0 1 r 1 * .. . .. . a 4 1 d 9 1 d 0 1 a 0 1 r 1 * .. . .. . a 4 1 d 9 1 h i gh - z x a 0 n r n * x .. . .. . a 4 n d 0 n - 1 a 0 n - 1 r n - 1 * .. . .. . a 4 n - 1 d 9 n -1 h i gh - z x d 0 2 a 0 2 r 2 * .. . .. . a 4 2 d 9 2 h i gh - z d 0 1 a 0 1 r 1 * d 9 1 .. . .. . a 4 1 d 0 n a 0 n r n * .. . .. . a 4 n d 9 n .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . x x c s s c l k s d i 1 s d o 1 s d i 2 1 0 1 1 1 2 1 6 d 0 n a 0 n w n * h i gh - z * w = 1 s d o n - 1 s d i n .. . .. . 1 1 0 1 1 1 2 1 6 .. . .. . 1 d 9 n .. . .. . a 4 n h i gh - z x x x a 0 2 .. . .. . a 4 2 w 2 * h i gh - z d 0 2 d 9 2 1 0 1 1 1 2 1 6 .. . .. . 1 d 0 2 a 0 2 w 2 * d 9 2 .. . .. . a 4 2 a 0 1 w 1 * .. . .. . a 4 1 d 0 1 d 9 1 a 0 3 .. . .. . a 4 3 w 3 * d 0 3 d 9 3 a 0 n .. . .. . a 4 n w n * h i gh - z d 0 n d 9 n s d o n h i gh - z x x x h i gh - z .. . .. . .. . .. . .. . max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
register map the max14001/max14002 registers and their default power-on-reset (por) values are shown in table 3 : table 3. register map * register is read only for the max14002 notes: 1: inrr = inrrv = 0x0c0 for max14002 2: inrt = inrtv = 0x180 for max14002 3: inrp = inrpv = 0x1d8 for max14002 4: setting iinr = 0 forces ifet = 50a 5: setting ibias = 0 forces ifet = 50a 6. x is unused. maxim integrated 21 addr name type purpose 9 8 7 6 5 4 3 2 1 0 default 0x00 adc r unfltered adc reading adc[9:0] 0x01 fadc r filtered adc reading fadc[9:0] 0x02 flags cor error flags x (6) mv fet crcf crcl com spi inrd adc x 0x000 0x03 flten rw fault enable x emv efet ecrcf ecrcl ecom espi einrd eadc dyen 0x1ff 0x04 thl rw lower comparator threshold thl[9:0] 0x100 0x05 thu rw upper comparator threshold thu[9:0] 0x200 0x06 inrr rw* inrush re-arm threshold (1) inrr[9:0] 0x0c0 0x07 inrt rw* inrush trigger threshold (2) inrt[9:0] 0x180 0x08 inrp rw* inrush pulse (3) iinr[3:0] (4) tinr[3:0] du[1:0] 0x1d8 0x09 cfg rw confguration ibias[3:0] (5) exrf exti ft[1:0] fast iraw 0x183 0x0a enbl rw enable x x x x x ena x x x x 0x000 0x0b act wc action inpls x rset sres x x x x x x 0x000 0x0c wen rw write enable wen[9:0] 0x000 0x0d-0x12 reserved reserved. do not use 0x13 fltv rw flten verifcation fltv[9:0] 0x000 0x14 thlv rw thl verifcation thlv[9:0] 0x2ff 0x15 thuv rw thu verifcation thuv[9:0] 0x1ff 0x16 inrrv rw* inrr verifcation (1) inrrv[9:0] 0x33f 0x17 inrtv rw* inrt verifcation (2) inrtv[9:0] 0x27f 0x18 inrpv rw* inrp verifcation (3) inrpv[9:0] 0x227 0x19 cfgv rw cfg verifcation cfgv[9:0] 0x27c 0x1a enblv rw enable verifcation enblv[9:0] 0x3ff 0x1b-0x1f reserved reserved. do not use max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
r - read only rw - read and write cor - latched read only, clear on read wc - write and clear (write only, executes and clears immediately) address = 0x02 default = 0x000 latched flags indicate errors and why the fault pin was asserted if the fault is enabled in the flten register. reading the register clears all flags. note: faults conditions are latched and the relevant bits are set; reading the value of this register will reset the fault flags that are not active anymore. however, if the fault is still valid, reading the flags register will not be able to clear the specific bit. address = 0x00 address = 0x01 register type legend: adc (read) fadc (read) flags (latched, clear on read) maxim integrated 22 register detailed description bit field name description 9:0 adc[9:0] contains the latest adc reading (straight binary) bit field name description 9:0 fadc[9:0] contains the latest fltered adc reading as set by bits ft[1:0] in the cfg register (straight binary) bit field name description 0 flag0 unused 1 adc adc reading stuck at one value 2 inrd exceeding specifed duty-cycle for the inrush current 3 spi number of bits clocked in while cs was asserted is not an integer multiple of 16 4 com field-side communication failure 5 crcl field-to-logic-side transmission had 6 consecutive crc errors reported 6 crcf logic-to-feld-side transmission had 6 consecutive crc errors reported 7 fet input voltage detected without input current 8 mv failed memory validation 9 flag9 unused max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x03 default = 0x1ff enables fault conditions to assert the faul t signal. note: fault enable bits only effect fault reporting through the fault pin. bits in the flags register will be set regardless whether fault is enabled or disabled by the flten register. address = 0x04 default = 0x100 user-programmed lower comparator threshold. when the output of the comparator is high, this value is compared to adc (or fadc as set by iraw, ft0 and ft1). if adc thl, the comparator output cout is set low. to prevent oscillation, the value of thl should be smaller than thu. thl (read/write) flten (read/write) maxim integrated 23 bit field name description 0 dyen 0: fault is latched; it is cleared after the flags register is read. 1: fault is dynamic; it is cleared as soon as the fault condition disappears. (default) 1 eadc 0: prevents adc error from asserting fault 1: allows adc error to assert fault (default) 2 einrd 0: prevents inrd error from asserting fault 1: allows inrd error to assert fault (default) 3 espi 0: prevents spi error from asserting fault 1: allows spi error to assert fault (default) 4 ecom 0: prevents com error from asserting fault 1: allows com error to assert fault (default) 5 ecrcl 0: prevents crcl error from asserting fault 1: allows crcl error to assert fault (default) 6 ecrcf 0: prevents crcf error from asserting fault 1: allows crcf error to assert fault (default) 7 efet 0: prevents fet error from asserting fault 1: allows fet error to assert fault (default) 8 emv 0: prevents mv error from asserting fault 1: allows mv error to assert fault (default) 9 flten9 unused bit field name description 9:0 thl[9:0] lower comparator threshold (straight binary) max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x05 default = 0x200 user-programmed upper comparator threshold. when the output of the comparator is low, this value is compared to adc (or fadc as set by iraw, ft0, and ft1). if adc thu, the comparator output cout is set high. to prevent oscillation, the value of thu should be larger than thl. address = 0x06 default = 0x0c0 user-programmed inrush timer re-arm threshold. adc reading must drop below this value before another inrush pulse will occur when the input voltage exceeds inrt. this register is not used in the max14002, which always uses fast mode (see bit 1 of the cfg register). address = 0x07 default = 0x180 user-programmed inrush current trigger threshold. when the inrush timer is armed, an inrush pulse is initiated when the adc reading equals or exceeds this value. this register is not used in the max14002, which always uses fast mode (see bit 1 of the cfg register). thu (read/write) inrr (read/write) (read only for max14002) inrt (read/write) (ready only for max14002) maxim integrated 24 bit field name description 9:0 thu[9:0] upper comparator threshold (straight binary) bit field name description 9:0 inrr[9:0] inrush re-arm threshold (straight binary) bit field name description 9:0 inrt[9:0] inrush trigger threshold (straight binary) max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x08 default = 0x1d8 contains user-programmed values for the inrush current pulse magnitude, inrush pulse duration, and inrush pulse duty cycle. inrp (read/write) (read only for max14002) maxim integrated 25 it field name description 1:0 du[1:0] du1 and du0 set the maximum duty cycle for inrush current over the last 10 seconds. du[1:0] = 00 duty cycle limiting function off (default) du[1:0] = 01 duty cycle = 1.6% du[1:0] = 10 duty cycle = 3.1% du[1:0] = 11 duty cycle = 6.3% 5:2 tinr[3:0] 4-bit inrush time, 0 to 120ms in 8ms steps, straight binary tinr[3:0] = 0000 = 0ms tinr[3:0] = 0001 = 8ms ........ tinr[3:0] = 0110 = 48ms (default) . tinr[3:0] = 1110 = 112ms tinr[3:0] = 1111 = 120ms 9:6 iinr[3:0] 4-bit inrush current, 50a to 105ma in 7ma steps, straight binary iinr[3:0] = 0000 = 50a iinr[3:0] = 0001 = 7ma ........ iinr[3:0] = 0111 = 49ma (default) . iinr[3:0] = 1110 = 98ma iinr[3:0] = 1111 = 105ma max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x09 default = 0x183 configuration register controls functions within the max14001/max14002. cfg (read/write) maxim integrated 26 bit field name description 0 iraw selects inrush comparator input multiplexer. 0: inrush comparator input is connected to fltered data in the f adc register 1: inrush comparator input is connected to raw data in the adc register (default) 1 fast selects fast inrush mode. adc is not used to trigger inrush. inrush starts as soon as suffcient voltage is present at high-voltage fet to provide the current. inrush timer is reset when there is not suffcient voltage to sustain the bias/inrush current. note: max14002 only works in fast inrush mode . 0: adc controlled (unused in max14002) 1: fast inrush mode (default) 3:2 ft[1:0] ft1 and ft0 control the number of readings that are averaged in the adc flter. ft[1:0] = 00 filtering off (default) ft[1:0] = 01 average 2 readings ft[1:0] = 10 average 4 readings ft[1:0] = 11 average 8 readings 4 exti connects the 70a current source to the refin pin. this current powers an external shunt voltage reference. 0: current source off (default) 1: current source on and connected to the refin pin (external shunt reference) 5 exrf selects the voltage reference source for the adc. 0: internal voltage reference enabled (default) 1: external voltage reference enabled 9:6 ibias[3:0] 4-bit bias current, 50a to 3.75ma in 0.25ma steps. this current fows through the high- voltage fet when not in inrush mode. ibias[3:0] = 0000 = 50a ibias[3:0] = 0001 = 0.25ma ........ ibias[3:0] = 0110 = 1.5ma (default) . ibias[3:0] = 1110 = 3.5ma ibias[3:0] = 1111 = 3.75ma max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x0a default = 0x000 the ena bit in the enbl register enables the inrush and bias current. at por, ena is set to 0. after programming all the configuration registers, the user sets ena to 1, which enables the ifet current sink. this procedure prevents unintentional currents from flowing during the configuration process. it is recommended to set this bit at the very end of the configuration procedure. address = 0x0b default = 0x000 immediate action register. when a bit is written to this register, action is taken immediately and the bit is then cleared. note: the sres bit (bit 6) resets only the spi registers while the rset bit (bit 7) is acting as the global por, the dc-dc converter will turn off and field-side will be reset as well as the logic-side (spi interface). address = 0x0c default = 0x000 write enable register. a value of 0x294 in this register enables writing to the spi registers. set to 0x294 prior to writing to any configuration or verification registers. set to 0x000 after configuring all registers. its purpose is to make it highly unlikely that any settings will be unintentionally changed by noise on the spi bus. note: this register should be reset to 0x000 after configuring the device prior to normal operation. enbl (read/write) act (write and clear) wen (read/write) maxim integrated 27 bit field name description 3:0 enbl[3:0] unused 4 ena 0: prevents the feld-side current sink (default) 1: enables the feld-side current sink 9:5 enbl[9:5] unused bit field name description 5:0 act[5:0] unused 6 sres software reset. restores all registers to their por value. 0: normal operation (default) 1: software reset 7 rset reset. has the same effect as a power on reset. 0: normal operation (default) 1: reset 8 act8 unused 9 inpls trigger an inrush current pulse. has no effect when ena = 0 (in the enbl register) 0: normal operation (default) 1: trigger an inrush current bit field name description 9:0 wen[9:0] this register must be set to 0x294 prior to writing to any spi registers. max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x13 default = 0x000 flten verification register. bits are continually compared to the flten register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of flten register por value. address = 0x14 default = 0x2ff thl verification register. bits are continually compared to the thl register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of thl register por value. address = 0x15 default = 0x1ff thu verification register. bits are continually compared to the thu register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of thu register por value. address = 0x16 default = 0x33f (0x0c0 for max14002) inrr verification register. bits are continually compared to the inrr register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of inrr register por value. note: this register is not used in max14002. default value is fixed at 0x0c0. bit field name description 9:0 inrrv[9:0] inrr verifcation register. bits are continually compared to the inrr register. fltv (read/write) thlv (read/write) thuv (read/write) inrrv (read/write) (read only for max14002) maxim integrated 28 bit field name description 9:0 fltv[9:0] flten verifcation register. bits are continually compared to the flten register. bit field name description 9:0 thlv[9:0] thl verifcation register. bits are continually compared to the thl register. bit field name description 9:0 thuv[9:0] thu verifcation register. bits are continually compared to the thu register. max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
address = 0x17 default = 0x27f (0x180 for max14002) inrt verification register. bits are continually compared to the inrt register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of inrt register por value. note: this register is not used in max14002. default value is fixed at 0x180. address = 0x18 default = 0x227 (0x1d8 for max14002) inrp verification register. bits are continually compared to the inrp register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of inrp register por value. note: this register is not used in max14002. default value is fixed at 0x1d8. address = 0x19 default = 0x27c cfg verification register. bits are continually compared to the cfg register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of cfg register por value. address = 0x1a default = 0x3ff enbl verification register. bits are continually compared to the enbl register. if any bits do not match, the mv bit in the flags register is set and fault is asserted if the emv bit in the flten register is set. por value is 1s complement of enbl register por value. inrtv (read/write) (read only for max14002) inrpv (read/write) (read only for max14002) cfgv (read/write) enblv (read/write) maxim integrated 29 bit field name description 9:0 inrtv[9:0] inrt verifcation register. bits are continually compared to the inrt register. bit field name description 9:0 inrpv[9:0] inrp verifcation register. bits are continually compared to the inrp register. bit field name description 9:0 cfgv[9:0] cfg verifcation register. bits are continually compared to the cfg register. bit field name description 9:0 enblv[9:0] enbl verifcation register. bits are continually compared to the enbl register. max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
figure 12. register programming for configuration of max14001/max14002 after power-on-reset maxim integrated 30 confguration flowchart power up wait 100 ms read flags 0 x 02 disable fault mv flten : emv = 0 write wen value = 0 x 294 write configuration registers determine error ( s ) ( except mv flag ) field side power up * flags = 0 x 100 ? y n write verification registers including flten , thl , thu , inrr , inrt , inrp , cfg including fltv , thlv , thuv , inrrv , inrtv , inrpv , cfgv enable fault mv write flten and fltev write wen value = 0 x 000 read back configuration registers normal operation write wen value = 0 x 294 write enbl : ena = 1 and enblv read flags 0 x 02 * flags = 0 x 000 ? determine error ( s ) write wen value = 0 x 000 enable spi registers write prevent mv flag from generating fault enable mv flag to generate fault disable spi registers write enable registers write enable field side current sink read to clear flags : mv bit flags : mv is set due to enbl and enblv write . disable spi registers write read flags 0 x 02 * flags = 0 x 000 ? determine error ( s ) verify system settings y n y n fault asserted flags : mv = 1 read flags 0 x 02 read to clear flags : mv bit read flags 0 x 02 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
max14002 vs. max14001 the max14002 is a reduced functionality version of the max14001. the max14002 only works in fast mode and does not limit the number of inrush pulses. in the max14002, write access is permanently disabled to three registers: inrr, inrt, and inrp. in addition to disabling write access to these registers, the three corresponding verification registers inrrv, inrtv, and inrpv will default to the same value as the configuration registers, and an mv fault in the flags register related to these registers is not generated during startup unless the memory is corrupted. all other functions are the same as the max14001. applications information typical application circuit the max14001/max14002 are designed for industrial configurable binary input applications. the input voltage on the field-side is continuously measured by the integrated adc, and results are transmitted across the isolation barrier and compared to the programmable high and low thresholds on the logic-side. the cout pin presents the real-time result of the comparison and notifies the system if the binary input is a logic-high/logic-low voltage level. the max14001/max14002 also provide current control through a high-voltage depletion mode fet. while the drain of the high-voltage fet is connected to the binary module input, the gate voltage of the fet is set at a nominal 3.6v by the max14001/max14002s gate pin. the ifet pin is connected to the source of the fet to sink a programmable inrush or bias current. when the binary module input voltage is higher than the trigger threshold, typically in the case of an external relay closing, an inrush current is triggered to clean the relay contacts. control of the inrush current allows the binary input module to be used in different pulse counting and relay monitoring applications. see the typical application circuit for connection between the devices and the high-voltage fet. these devices are configured and monitored through an spi interface. the fault output can be configured to generate an interrupt when certain errors are detected by the embedded self-diagnostic circuit. fault is an open-drain digital output so an external pullup resistor is needed, typically 4.7k. layout, grounding and bypassing power supply recommendations it is recommended to decouple both the v dd and v ddl supplies with 10f capacitors in parallel with 1000pf capacitors to gndl. place the 1000pf capacitors as close to v dd and v ddl as possible. it is preferred to decouple the v dd pin through the gndl pin 11, and the v ddl pin through the gndl pin 19. the v ddf pin is the integrated dc-dc converter output and it is recommended to decou - ple it with low-esr capacitors of 0.1f in parallel with 1000pf to gndf (pin 10). place the 1000pf capacitor as close to v ddf as possible. for best performance, bypass the gate pin to the gndf plane with a low-esr capacitor of 0.01f and bypass the ifet pin to the gndf plane with a low-esr capacitor of 1000pf. refin is the optional external voltage reference input, and, for best performance, bypass refin to agnd with a 0.1f ceramic capacitor when an external voltage reference is used. refer to the typical application circuit for a connection example. layout considerations it is recommended to design an isolation or keep-out channel underneath the max14001/max14002 that is free from ground and signal planes. any galvanic or metallic connection between the field-side and the logic- side defeats the isolation. ensure that the decoupling capacitors between v ddl , v dd and gndl and between v ddf and gndf are located as close as possible to the ic to minimize inductance. route important signal lines close to the ground plane to minimize possible external influences. on the field-side, it is good practice to separate the adc input and voltage reference ground agnd from the gate and ifet reference ground gndf. maxim integrated 31 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
high-voltage fet the max14001/max14002 are designed to use a low cost, readily available high-voltage depletion mode fet as the external high-voltage power device. the high voltage binary input is connected to the fets drain while the gate and source are at low voltages compatible with the max14001/max14002. the fet is driven in a cascade fashion with its gate held at a constant voltage by the gate pin. the ifet pin sinks the specified inrush or bias current from the fets source and in the process modulates the fets source voltage. refer to the typical application circuit for a connection example. the max14001/max14002 need at least 1v on the ifet pin under worst-case conditions. with a typical voltage of 3.6v, the gate pin provides a maximum v gs of 2.6v to the fet. the required maximum fet on resistance r on can be calculated as: r on (v drain - v ifet )/i inrush where i inrush can be configured to 105ma maximum and v ifet = 1v. for example, if the fet v drain = 24v, the maximum r on is calculated to be 219 at v gs = 2.6v. when selecting the fet, temperature tolerance should also be taken into consideration. for applications where the peak input voltage does not exceed 600v, it is recommended to use the following devices: infneon bsp135 ixys ixty08n100d2 maxim integrated 32 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
maxim integrated 33 typical application circuit 1 . 7 1 v to 5 . 5 v 3 . 0 v to 3 . 6 v r p u l l - up v d d gp i gp i cs s c l k m os i m i s o 1 2 0 k g n d f 10 0 0 p f gn d f gn d f d e p l e ti on m od e fe t v i n gn d f fi e l d s i d e log i c s i d e v d d l v d d fault c ou t cs s c l k s d i s d o g n d l g n d f v d d f i s e t i c ga te i fe t r e fi n a i n a gn d m a x 140 0 1 / m a x 140 0 2 s p i h os t a gn d g n d i n te r n a l v r e f gn d l 10 0 0 p f 1 0 f gn d l 10 0 0 p f 1 0 f gn d l 10 0 0 p f 0 . 1 f gn d f a gn d 0 . 0 1 f ordering information chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package MAX14001AAP+ -40c to 125c 20-ssop max14002aap+ -40c to 125c 20-ssop package type package code outline no. land pattern no. ssop-20 a20ms-6 21-0056 90-0094 max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs www.maximintegrated.com
? 2016 maxim integrated products, inc. 34 revision history revision number revision date description pages changed 0 5/16 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max14001/max14002 confgurable, isolated 10-bit adcs for multi-range binary inputs for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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